The present invention relates to a structure of a semiconductor device suitable for enhancing integration density and high performance, and its manufacturing process. More particularly, the present injection type semiconductor devices.
In accordance with the increasing capacities in VLSIs typified by DRAMs, it is required for the semiconductor devices to be implemented therein to have a highly dense integration structure. A number of problems, however, have arisen with such efforts to increase integration densities as will be discussed below.
For example, regarding MOSFETS, which are the typical semiconductor devices, further reduction in dimension is considered difficult to realize because of the following: (1) variations in characteristics due to the short channel effect, (2) decrease in withstand voltage due to the parasitic bipolar effects, (3) possible threshold voltage variation due to the statistical fluctuation of impurities, (4) an increase in a leakage current due to the increased impurity concentration, and so on.
One of the ways to solve the above-mentioned problems above, has been proposed in Japanese Patent Publication No. 62-274775 (1987), wherein a tunneling current flowing through the Schottky barrier junction is controlled by means as set forth therein.
The aforementioned prior art semiconductor device utilizing the prior art tunneling current control techniques has an unsymmetrical structure which is rather difficult to fabricate. Specifically, in this device the source is formed of metal while the drain is formed of an n.sup.+ -semiconductor layer. In addition, another arises because a connection wiring from said n.sup.+ -layer must be extended through the contact hole to the electrode wiring layer, thereby lengthening a carrier path. Further, contact resistance added up between the n.sup.+ -layer and the wiring causes the parasitic resistance to increase, thereby decreasing the drain (tunneling) current.